Programmable logic devices (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (“FPGA”), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, digital signal processing blocks (“DSPs”), processors, clock managers, delay lock loops (“DLLs”), and so forth. Notably, as used herein, “include” and “including” mean including without limitation.
One such FPGA is the Xilinx Virtex® FPGA available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124. Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include but are not limited to these exemplary devices, as well as encompassing devices that are only partially programmable.
For purposes of clarity, FPGAs are described below though other types of PLDs may be used. FPGAs may include one or more embedded microprocessors. For example, a microprocessor may be located in an area reserved for it, generally referred to as a “processor block.”
It should be understood that flip-chip and ball grid array packaging generally do not have exposed leads for probing. Thus, to do real-time debug and verification of a design instantiated in an FPGA, a tool called ChipScope from Xilinx, Inc., may be used. ChipScope facilitates debug and verification at or near operating system speed. Essentially, logic analyzer, bus analyzer, and virtual input/output low-profile software cores are loaded into programmable logic of an FPGA in addition to the instantiated design. These cores allow viewing of internal signals and nodes as brought out through a programming interface, and such signals may be captured for output at or near operating system speed. The FPGA may be linked to test bench equipment for signal viewing and analysis.
However, it should be appreciated that a software core solution, such as the ChipScope solution, is for testing while coupled to a “test bench” or other test equipment. Accordingly, it would be desirable and useful to provide means for testing or monitoring a design instantiated in a PLD while in an in-system operating environment for signal analysis.